fn481 rev.7.00 page 1 of 4 december 15, 2011 fn481 rev.7.00 december 15, 2011 ca-3083 general purpose high current npn transistor array datasheet the CA3083 is a versatile arra y of five high current (to 100ma) npn transistors on a c ommon monolithic substrate. in addition, two of these transistors (q 1 and q 2 ) are matched at low current (i.e., 1 ma) for applications in which offset parameters are of special importance. independent connections for each transistor plus a separate terminal for the substrate permi t maximum flexibility in circui t design . features ? high i c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100ma (max) ?low v ce sat (at 50ma). . . . . . . . . . . . . . . . . . . 0.7v (max) ? matched pair (q 1 and q 2 ) -v io (v be match). . . . . . . . . . . . . . . . . . . . . ? 5mv (max) -i io (at 1ma) . . . . . . . . . . . . . . . . . . . . . . . . 2.5 ? a (max) ? 5 independent transistors plus separate substrate connection ? pb-free plus anneal available (rohs compliant) applications ? signal processing and switching systems operating from dc to vhf ? lamp and relay driver ? differential amplifier ? temperature compen sated amplifier ? thyristor firing ? see application note an5 296 applications of the ca3018 circuit transisto r array for suggested applications pinout CA3083 (pdip, soic) top view ordering information part number part marking temp. range (c) package pkg. dwg. # CA3083 CA3083 -55 to 125 16 ld pdip e16.3 CA3083z (note) CA3083z -55 to 125 16 ld pdip* (pb-free) e16.3 CA3083m96 3083 -55 to 125 16 ld soic tape and reel m16.15 CA3083mz (note) 3083mz -55 to 125 16 ld soic (pb-free) m16.15 CA3083mz96 (note) 3083mz -55 to 125 16 ld soic (pb-free) tape and reel m16.15 *pb-free pdips can be used for through hole wave solder process ing only. they are not intended for use in reflow solder processing applications. note: intersil pb-free plus anneal products employ special pb-fr ee material sets; molding compounds /die attach materials and 100% matte tin plate termination finish, which are rohs compliant and comp atible with both snpb and pb-free soldering operations. intersil pb-fr ee products are msl classified at p b-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 substrate q 1 q 2 q 3 q 4 q 5
ca-3083 fn481 rev.7.00 page 2 of 4 december 15, 2011 absolute maximum ratings thermal information the following ratings apply for each transistor in the device: collector-to-emitter voltage, v ceo . . . . . . . . . . . . . . . . . . . . . . 15v collector-to-base voltage, v cbo . . . . . . . . . . . . . . . . . . . . . . . . 20v collector-to-substrate voltage, v cio (note 1). . . . . . . . . . . . . . 20v emitter-to-base voltage, v ebo . . . . . . . . . . . . . . . . . . . . . . . . . . 5v collector current (i c ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100ma base current (i b ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20ma operating conditions temperature range. . . . . . . . . . . . . . . . . . . . . . . . . .-55c to 125c thermal resistance (typical, note 2) ? ja (c/w) ? jc (c/w) pdip package . . . . . . . . . . . . . . . . . . . 135 n/a soic package . . . . . . . . . . . . . . . . . . . 200 n/a maximum power dissipation (any o ne transistor) . . . . . . . 500mw maximum junction temperature (plastic package) . . . . . . . 150c maximum storage temperature range . . . . . . . . . -65c to 150c maximum lead temperature (soldering 10s) . . . . . . . . . . . . 300c (soic - lead tips only) caution: stresses above those listed in ?abs olute maximum ratings? may cause permanent dam age to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. notes: 1. the collector of each transistor of the CA3083 is isolated fr om the substrate by an integral diode. the substrate must be co nnected to a voltage which is more negative than any collector voltage in order to m aintain isolation between transistors and provide normal transi stor action. to avoid undesired coupling between transistors, the substrate ter minal (5) should be maintained at either dc or signal (ac) grou nd. a suitable bypass capacitor can be used to establish a signal ground. 2. ? ja is measured with the component mounted on an evaluation pc boa rd in free air. electrical specifications for equipment design, t a = 25c parameter symbol test conditions min typ max units for each transistor collector-to-base breakdown voltage v (br)cbo i c = 100 ? a, i e = 0 20 60 - v collector-to-emitter breakdown voltage v (br)ceo i c = 1ma, i b = 0 15 24 - v collector-to-substrate breakdown voltage v (br)cio i ci = 100 ? a, i b = 0, i e = 0 20 60 - v emitter-to-base breakdown voltage v (br)ebo i e = 500 ? a, i c = 0 5 6.9 - v collector-cutoff-current i ceo v ce = 10v, i b = 0 - - 10 ? a collector-cutoff-current i cbo v cb = 10v, i e = 0 - - 1 ? a dc forward-current transfer ratio (note 3) (figure 1) h fe v ce = 3v i c = 10ma 40 76 - i c = 50ma 40 75 - base-to-emitter voltage (figure 2) v be v ce = 3v, i c = 10ma 0.65 0.74 0.85 v collector-to-emitter saturation voltage (figures 3, 4) v ce sat i c = 50ma, i b = 5ma - 0.40 0.70 v gain bandwidth product f t v ce = 3v, i c = 10ma - 450 - mhz for transistors q 1 and q 2 (as a differential amplifier) absolute input offset voltage (figure 6) |v io |v ce = 3v, i c = 1ma - 1.2 5 mv absolute input offset current (figure 7) |i io |v ce = 3v, i c = 1ma - 0.7 2.5 ? a note: 3. actual forcing current is vi a the emitter for this test.
ca-3083 fn481 rev.7.00 page 3 of 4 december 15, 2011 typical performance curves figure 1. h fe vs i c figure 2. v be vs i c figure 3. v ce sat vs i c figure 4. v ce sat vs i c figure 5. v be sat vs i c figure 6. v io vs i c (transistors q 1 and q 2 as a differential amplifier) v ce = 3v collector current (ma) dc forward current transfer ratio t a = 0c t a = 25c 0.1 1 10 100 60 50 70 80 90 100 t a = 70c v ce = 3v collector current (ma) base-to-emitter voltage (v) t a = 70c t a = 25c 0.1 1 10 100 0.6 0.5 0.7 0.8 0.9 t a = 0c h fe = 10, t a = 25 o c collector current (ma) collector-to-emitter 1 10 100 0.2 0 0.4 0.6 0.8 1 maximum typical saturation voltage (v) collector current (ma) collector-to-emitter 110100 0.2 0 0.4 0.6 0.8 1 1.2 maximum h fe = 10, t a = 70c typical saturation voltage (v) h fe = 10, t a = 25c collector current (ma) base-to-emitter 110100 0.6 0.5 0.7 0.8 0.9 1 saturation voltage (v) v ce = 3v, t a = 25c collector current (ma) absolute input offset voltage (mv) 0.1 1 10 1 0 2 3 4 5 6
fn481 rev.7.00 page 4 of 4 december 15, 2011 ca-3083 intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description on ly. intersil may modify the circuit design an d/or specifications of products at any time without notice, provided that such modification does not, in intersil's sole judgment, affect the form, fit or function of the product. accordingly, the reader is cautioned to verify that datasheets are current before placing orders. information fu rnished by intersil is believed to be accu rate and reliable. however, no responsib ility is assumed by intersil or its subsidiaries for its use; nor for any infrin gements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com for additional products, see www.intersil.com/en/products.html ? copyright intersil americas llc 1998-2011. all rights reserved. all trademarks and registered trademarks are the property of their respective owners. figure 7. i io vs i c (transistors q 1 and q 2 as a differential amplifier) typical performance curves (continued) v ce = 3v, t a = 25c collector current (ma) absolute input offset current ( ? a) 0.1 1 10 1 10 0.1
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